
module ASK_Modulator
#(
    parameter STAGE         =   2,
    parameter CARWIDTH      =   8,
    parameter WIDTH         =   10,
	parameter DEPTH			=		16,
	parameter Fmclk=65000000
)
(
    input wire [STAGE-1:0] i_DataInput,
    input wire i_clk,
    input wire i_rst,
    input wire [63:0] i_CarrierFreq,
    output wire [DEPTH-1:0] o_WaveAddr,
    input wire signed [CARWIDTH-1:0] i_Carrier,
    output wire signed [WIDTH-1:0] o_ASK_Signal
);

wire [WIDTH-1:0] exp_data;
wire signed [WIDTH-1:0] exp_carrier_iwid;
wire signed [(2*WIDTH):0] exp_carrier;
wire signed [(2*WIDTH):0] MulOut;
wire [DEPTH-1:0] DDS_fctrl;
assign 	DDS_fctrl=(i_CarrierFreq << DEPTH) / Fmclk;

assign exp_carrier_iwid={i_Carrier,{(WIDTH-CARWIDTH){i_Carrier[0]}}};
assign exp_carrier={{(WIDTH){exp_carrier_iwid[WIDTH-1]}},exp_carrier_iwid};
assign exp_data={{(WIDTH-STAGE){1'b0}},i_DataInput};
assign MulOut=(exp_carrier*(i_DataInput<<(WIDTH-STAGE+1))>>(STAGE-1));

DirectDigitalSynthesizer 
#(
    .DEPTH(DEPTH)
)
DDS_CarGen
(
    .i_freq_ctrl(DDS_fctrl),
    .i_phas_ctrl(0),
    .i_clk(i_clk),
    .i_rst(i_rst),
    .o_WaveAddr(o_WaveAddr)
);

assign o_ASK_Signal=MulOut[(2*WIDTH)-1:WIDTH];

endmodule